cRIO CAN 985x, Reset and TimeStamp after bus off

[pierreR]

Hello ,I'm working on a HIL project that's able to manage 5 CAN bus using cRIO in order to be able to restart quickly the communication after a bus off state.My question is easy :) . After a bus off , in order to restart the communication, it's needed to : Reset the SJA, reapply my Transceiver config and START it. My problem is the following, after a reset, the transceiver timestamp is erased. All my system : DAQ, LIN, CAN ... is synchronised by a pulse on RTSI0 that allow me to synchronise all my elements. The problem is that after a reset my CAN is no more synchronized, and the timestamp is not valid with the rest of the system.A workaround that I use for the moment is to have my own SCTL(10MHz) that generates TimeStamp since the pulse on RTSI0 and I systematically replace the SJA TimeStamp in my CAN Data by this timestamp, but for me it's not a really good solution.do you have any idea ?Best regards,Message Edité par pierreR le 06-26-2008 04:12 PM

[Maxime MULLER]

Hi Pierre :smileyvery-happy:,
I guess there isn't any other solution to the issue you are experiencing. I didn't find informations about this, except this KB : <a href="http://digital.ni.com/public.nsf/allkb/F435AC480BEC979F86257364005888FE?OpenDocument" target="_blank">Synchronization with NI 985x cRIO CAN</a>&nbsp;, but you may have already seen it. I'll have a better look&nbsp;at it this&nbsp;time&nbsp;next week and&nbsp;I'll keep you in touch.
Best regards,

[pierreR]

Hi Maxime, I saw this example, but in my case, I don't have an offset between my processes until a bus off on one of my CAN port. My workaround with an SCTL which is counting is working, but I wanted to know if someone has a better way.I sent an email to Ian Fountain the RT&amp;FPGA BDM for Europe. I hope I'll have an answer on monday.Thanks, and have a good day Bye bye